7. Technical Marketing

There is not a whole lot of real technical information available about Banias as yet. The most interesting snippet for most of you might be the fact that Banias will have a rather large second level cache (L2) of 1 MByte. As usual, the large cache is meant to make up for the difference between processor and memory clock. Banias uses a special low-power version of Pentium 4's good old 100 MHz quad-pumped processor bus, dubbed "400 MHz PSB." Like Pentium 4, Banias will also feature the SSE2-extensions to its instruction set.

Besides those few facts, here are some key words fresh from Intel's marketing department. So far, Intel has failed to supply any educationally valuable information, which is why I won't waste your time with some half-hearted explanations or guesswork.

The eight-way associative L2-cache of Banias is divided into four power quadrants per way, allowing to "shut off" those quadrants that are not being accessed, thus powering only 1/32nd of the L2-cache at a time, while the rest of the L2-cache is "sleeping." Other design optimizations reduce L2-gate power leakage.

Supposedly, 20% reduction of misprediction (but Intel doesn't say over which previous design...).

Sounds interesting. The CPU decoder makes several Micro-Ops out of a machine instruction and this new technology reverses this task..? So far, Intel has failed to give details.

All those features are supposed to ensure that Pentium-M has an "average power consumption" of less than 1 W, while still delivering satisfying performance.

In summary, one can say that the information Intel provided so far makes it very interesting to see how Banias compares against Pentium 4-M in terms of performance. Pentium M is clocked lower than Pentium 4-M and it seems to have more new features that improve power consumption than features that improve processor performance. Will Pentium M be able to stand up against its predecessor?