6. Pentium M: The CPU Optimized For Working On The Move

Hitherto, Intel has used the following recipe in development of its mobile processors: take the desktop CPU architecture (Pentium III or Pentium 4), select the dies according to power consumption (low power consumption = mobile processor "embryo"), and garnish the whole with energy-saving techniques such as Enhanced Speedstep, Deeper Sleep and IMVP. And there you have a mobile CPU that, in principle, is nothing more than a desktop processor optimized for the task at hand.

In developing the Pentium M, on the other hand, Intel's Israeli development team under Mooly Eden has staked everything on designing the production process and the CPU architecture to be as thrifty power-wise as possible - without sacrificing too much performance. This makes the Pentium M (Banias) the first "genuinely" mobile CPU from Intel, not a direct rehash of a desktop CPU like all its predecessors.

The only features the Pentium M and the Pentium 4-M really share are the manufacture using 0.13µm technology and the fact that the processor system bus works with 100 MHz quad-pumped and thus has bandwidth of 3.2 GB/s at its disposal.

A look at the cache architectures of both CPUs makes the differences clearer.

The Pentium M has a 32 kB L1 cache each for data and commands, and not a trace cache like the Pentium 4-M. The L1 data cache in the Banias is not only four times as large, but, thanks to the write-back write strategy it uses, it also functions more effectively than that in the Pentium 4-M (write-through write strategy). Because of its markedly higher speed, the L1 data cache used in the P4-M offers extremely short access times.

At 1 MB, the L2 cache in the Banias is twice as large as the one in the Pentium 4-M. Theoretically, it should consume double the amount of power. To prevent this, the developers came up with "intelligent" wiring.

The eight-way set-associative L2 cache is split into four sectors per way and is thus divided into 32 segments altogether. When accessed, the cache logic ensures that only one addressed segment (32 kB) is active at any one time. The rest of the cache is inactive during this time and only consumes standby power. Although "waking up" the individual segments raises access time by a clock cycle, this is obviously compensated for with the L2 cache's size. This means that an L2 cache along these lines uses substantially less power.

In addition, a polished design and an improved production process have enabled considerable reductions of leakage currents in the memory, data paths, the TAG RAM and the control logic. This measure alone saves more than a watt in dissipation.

Besides the cache segments, numerous others of the processor's logical units can be switched off if they are momentarily not needed for program execution. Intel calls this energy-saving technology "fine-grain hardware gating." The I/O voltage of the processor system bus (PSB) is just 1.05 volts and thus clearly below the 1.3 volts of the Pentium 4-M. Even the Banias' input amplifier can be switched off with the chipset's support if necessary - when the processor is not receiving data. So that nothing goes missing, data are temporarily stored in dynamic buffers. If the processor starts receiving data again, the i855 chipset uses the DPWR# control circuit to reactivate the processor's input driver.