Intel users - all ignorant and uninformed! - Page 2
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| Quote : The Athlon XP got copper interconnects, i believe, and also these "below 0.18 micron" gate designs at various places, according to Intel. |
The gate lengths were smaller, this is sign of a refined process, NOT a direct relation to process size, also the tbird had copper ics already.
| Quote : The Athlon architecture was never designed for really high speed in the same way as the P4, and I think that AMD was foorced to implement "below 0.18 micron" in order to push it further than 1400MHz. |
Raystonn said himself the p3 was designed to top out at 1ghz, and now the tually can reaCH 1.6GHZ, we dont even know what speed the axp was designed to run, but I guarentee you it is not near the limits of its design by a longshot. The p4's intrinsic advantage has already been accounted for in the fact that while it gains 655-65% top speed, it is gaining it from 2.2ghz putting them roughly at 3.5ghz+, whil;e a 55% gain on the axp will put it around 2.4ghz or so, probably more, which is much slower in pure clock than the p4.
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| Quote : Are you sure about the Tbird having copper? I remember talk of Dresden Tbirds having copper and the others not, but I think that rumor was laid to rest and copper interconnects came with the XP. |
Dresden tbirds did in fact have copper, austin tbirds did not, sorry for not clarifying.
It is DIFFICULT IN THE EXTREME for a fab to use both copper and aluminum, so if dresden was set up for copper than while it is possible it also had aluminum as well, it is HIGHLY unlikely(copper is a hugely dirty process and it contaminates everything in a fab, and if copper gets in your alumimnum tools you have a problem).
Further evidence can be seen in the top speed of an austin tbird is about 1ghz, where a dresden tbird is 1.4ghz, the difference in fab quality can hardly explain a 40% difference in top speed on the same core. The answer is copper.
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| Quote : Eden, I'm not trying to make Intel look better than AMD, I'm just trying to guess why:
|
1) so was the northwood, was intel using .13 micron tech in its processors which caused it to be LATE as well?(moral, dont jump to conclusions)
2) if they are having trouble with the shrink OFCOURSE the first samples will not overclock well, which would also explain 1 above.( and I do believe they had a problem with the shrink, but texas techie hears they know whats wrong and have fixxed it, it does take 2 months + for a chip to get from start to finish in a fab)
3. Yes and no, the .13 CLASS gate lengths are not a direct relation to process size, and they DID give a performance advantage, but even if amd shrunk the process AND kept the same gatelength, the loss in top speed % would be VERY SMALL, the MAIN gains from a process shrink are lower heat and less current needed in the lines, period, gate lengths which are lower allow faster switching transistors, but very few transistors in a cpu are switching on and off near their max limit, the heat of the whole system keeps the clockspeed down low enough where thats not a major concern.
If I am making sense to you.
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| Quote : 1. The performance & frequency increase from Cu-mine to Tully benefit from copper interconnection in addition to 0.18-> 0.13 shrink. AXP-> T-Bred is purely a shrink, so I donot expect the improvement will be that impressive;
|
1: this is true, and I agree which is why I estimate a 40% top speed gain for the axp instead of the tuallys 55%.
2: There were reports of the very first tuallys released hitting 1.6-1.7ghz, this was not a refined tually, the tually celersons dont hit as high, but I would attribute that to intel doing something to them personally.
When I made my prediction I took all these things into account, I also took into account amds superior gatelengths and their better design(as compared to the p3). So I stand by my prediction that the tbreds top speed will go up by 40-50% in the .13 micron shrink.
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Yeah MOD, lol, sorry
I had been reading the FatBurger challenge thread all the way through, and I clicked into this one and walked away for a sec. When I came back my memory must have lapsed...
Sorry! 
Mmmm... <font color=red>Red Hot</font color=red>
| Quote : 40% equals 2520 MHz
|
They have ALREADY demoed a 2800+ chip, is another 200mhz so hard to believe>?>????
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| Quote : I that holds true, AMD will not even need the Hammer to finish off Intels current P4. AMD could then hold back the Hammer until Prescott turns up. Somehow I find those numbers hard to believe. |
This will be the END of the tbred, whereas the hammer supposedly will BEGIN at 3400, I can fully see a pr3000 tbred leading to the 3400 hammer.
And while the numbers may be hard to believe I have yet to hear a physical reason why that is.
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| Quote : I belive AMD refined their gates, or whatever, to raise the max obtainable frequency, but again, I'm just wild guessing. |
The refining of the gates was most likely a side effect of a good process, not a goal they set forth, when your fab is tight and you constantly meat your spc goals, you can begin to tighten specificatons, the gatelength is one of the first things you can tighten(that and gox thickness) without requiring retoooling, sure there is a benifit, but the benifit is not the same as the core gains from a die shrink would achieve.
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Yep, top speed, which MAY OR MAY NOT, be available immediatly, there will be tweaking there will be refinment, but I do stand by my TOPSPEED claims.
As for the overclockability over stock, I did only say the 55% would be for a downbinner amd, so pepper is right there.
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I think the delay is because their first steppings were not clocking well and they discovered a timing issue, they resolved the issue but it STILL TAKES 2-3 MONTHS for the corrected chips to come off the line.
I work(ed unemployed right now) in a fab, I know how these things work.
The gains from a process shrink are nearly universal independant from core design. The p3 gains 50-60% due to a shrink AND COPPER, the p4 gains about 50-60% from a shrink AND COPPER, the amd will gain about 40-50% from the shrink BUT THEY ALREADY HAVE COPPER.
LOok, this is an educated guess, I think I am right, but I really really want some logical reasoning which disagrees with me, only ray has tried(and was wrong) but I really want to get to the bottom of it and look at it logically.
There is one monkeywrench which is if the gatelengths DO have a huge impact, but everything I know about semiconductors(and I do know quite a bit, its my job) says this is not the case.
So I welcome a discussion and discourse, and I hope people can share their knowledge or things they have read which will possibly cause me to modify my theory to fit the data.
if anyone wants to chat real time Im in chat.classicrpg.com right now and I would love to discuss.
Matt
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| Quote : So let me get this straight:
|
Yep
| Quote : BTW is Fugistsu a supplier for fabs for AMD's chips? If not, then what chip fabs you were mostly working in? |
Fujitsu was a flash partner with amd, although our fab didnt do logic we did flash and dram, the process is the same but logic has more metal layers and is more complex(but less dense).
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| Quote : Would the max clock speed change if a company converted from 0.18m and skipped directly to 0.09m? I was wondering maybe if they would pass through the 0.13m first, they would squeeze to max, instead of stand by theoretical speeds, and then jump to 0.09m, thus in total from 0.18m times to 0.09m the max clock speed was higher than the one if they had skipped through 0.13m and went directly to 0.09m. |
Assuming you had no issues the net gain would be the same, a process will top out at a certain speed on a process size regardless of refinement. (although refinement may gain you some top speed it will always be bested by a shrink.
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Process refinement usually deals with thickness, gateox thickness ild thickness, things you can tweak while still using the same feature size.(gate length etc etc)
A process shrink is when you shrink down the lines etc to a smaller average distance, this is a major thing and usually requires retooling and a reassignment of control parameters.
If my control target is .5nm and I have an upper control limit of 6 and lower is better, if all of the widgets I make start to always hit below 5(if one goes over 6 I look for a problem in my line).
Once all of the controls hit their targets and start exceding them, I can then lower the targets, thus when a widget has a 5 now(which was my target before but now its say 4) I will begin to look for a root cause of the problem and remedy the issue, this overtime causes refinement of the process.
INtel claimed that amd had .13micron CLASS gate lengths, that is their.18 micron gate lengths were below what you would expect to find for a .18 micron process and were at the levels you would expect for a .13 micron process. Now if dresden were designed from the ground up as I have heard to be a .13 fab, then there is ample reason to conclude that the gate lengths which were small were a result of the improved etching and thinfilms process that dresden had, rather than a concious effort on amds part, which is extremely believable.
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Matisaro, could you enlighten me by explaining exactly WHAT the 0.13micron (0.18, 0.09...) refers to? Is it the absolutely smallest feature in the microprocessor, the gate-length, or what is it?
Also Eden, regarding your hypothetical question about skipping the 0.13micron step: just want to say that obtaining reliable features of size about 2/3 of the current technology is freakin' difficult, so skipping a step isn't that realistic.
Ile lente.
<b><font color=blue>gnintsakgnirkskir ksron</font color=blue></b>
I don't think so: a 130nm feature is SMALL; the atomic spacing of Silicon is about 0.25nm, so 130nm should correspond to about 500 atoms per feature. This might not sound to impressive, but remember that atoms in a crystal lattice may diffuse away from their intended configuration rather easily, whether they're stuck in the bulk or on a surface, especially with increased temperature and mimimized feature sizes.
I have the feeling that "130nm" features describes the smallest "dip" or "mesa" within each transistor; not the total size of the transistor themselves. Sort of like why internet speeds like 56KB per second means 56 Kbits per second, and not 56 Kbytes per second, which is the common measure of speed.
<b><font color=blue>gnintsakgnirkskir ksron</font color=blue></b>
A common way to make features on a semiconductor surface is to first coat the surface with a photoresist, a polymer based liquid that hardens onto the surface and makes a film that is some 10-100nm thick, depending on how fast you spin it on, and what exact photoresist you use. This resist is then illuminated with an electron beam or a UV lamp (again, depending on the process), through a predefined mask, and the pattern left in the resist is NOT square, but rather rounded (most intense in the middle of where the beam/light hits, and less intense on the sides (Gaussian distribution, approximately).
surface:
________________________
................\...exposed../................
resist.........\..resist.../.......resist..
_________\ ___/__________
Silicon
...
(hard to draw with ASCII characters... 
I needed the dots to make the spacing right)
You now take the semiconductor WITH the exposed resist through a development procedure that removes the exposed resist and leaves a rounded hole in the resist.
Next step is to put this through an etching process, which can be done by either 1) a chemical etch using some acid that attacks Silicon, but not the resist (or at least, not as fast); but the result of a "wet-etch" is often not desireable: it'll etch up against a crystal facet, and will most often NOT make square holes. Another approach is 2) a plasma-etching process (ECR), where a plasma is excited above the surface in a chamber filled with some combination of gases (Chlorine and Boron work for Gallium Arsenide; not sure about Si), and this approach can then be tuned to make pretty nice square holes, which is what you want.
The problem, of course, is that the size of the hole defined by the photoresist (drawn above) is very sensitive to the thickness of the resist, the intensity of the beam and the time of exposure. I'm sure that the semiconductor industry has this all tuned very nicely, but believe me, it's tricky stuff.
All this is to say that in order to make "90nm features" requires very thin resist films, very carefully tuned exposure steps and very carefully calibrated etching steps.
<b><font color=blue>gnintsakgnirkskir ksron</font color=blue></b>
Hmm, no, a wafer is just a thin pancake cut out of a long piece of Silicon. There's nothing in there but *pure* Silicon (as pure as possible). A transistor is like a LEGO construction on top of this wafer, composed of different layers of semiconductors, metals (for electrical contact) and insulators (for NO electrical contact). The difference between LEGO and semiconductor fabrication is that 1) Denmark has nothing to to with the latter and 2) there are no predefined pieces to put together in order to make a chip (or the transistors that it's composed of).
As outlined in the post above, you also need lateral features on your chip (it's not enough to just put down layers of different semiconductors, insulators and metals).
The film-growth is done in an MBE (molecular beam epitaxy) or an MOCVD (metallorganic chemical vapor deposition). You take your flat (hopefully) Si-wafer and stick it into one of these machines, and in the case of MBE, you evacuate the chamber (to high vacuum), heat up the wafer, and then heat up crucibles of various elements (whatever you want to grow on top of the wafer). The material in the crucible evaporates and a beam of indivual atoms is thrown towards the surface (simply speaking). The atoms hits the surface and roam around on it for a little while before it finds a place on the surface that it finds favourable (perhaps next to an Si atom that's already there). This is how the crystal structure continues into the deposited film: by slowly adding new atoms onto an already defined lattice.
<b><font color=blue>gnintsakgnirkskir ksron</font color=blue></b>
I'm not sure how the pipeline fits into it all... Does it increase the spacing between each transistor, although the transistors themselves might be small? It doesn't make much sense, but it could be true, I suppose...
By decreasing the size of the transistors, you decrease the travel time of electrical signals between the different transistors (faster processors), AND you can fit a given amount of transistors into a smaller space (smaller chips, or more chips per wafer: cheaper processors!)
Decreasing the transistor sizes would always be advantegous, as long as you don't run into problems with too hot chips that'll destroy the chips (essentially by "melting" the chip by diffusion of individual atoms in the chip).
[-peep-], how do you spell "advantegous"? Is this correct?
<b><font color=blue>gnintsakgnirkskir ksron</font color=blue></b>
------------------------------------------------------------------
[-peep-], how do you spell "advantegous"? Is this correct? ---------------------------------------------------------
---------
i didn't know that THG censored nasty words!!! in my post above, i certainly didn't say [-peep-]! heheee...
thanks on the speling
<b><font color=blue>gnintsakgnirkskir ksron</font color=blue></b>
Can anyone explain how the length of the pipeline affects the size of the transistor, or the size of the processor?
<b><font color=blue>gnintsakgnirkskir ksron</font color=blue></b>
| Quote : Top speed Athlon XP could do 1800MHz. AMD Throughbred demo showed 2200MHz. That's a decent 400MHz increase. And now you want me to believe they can push it another 590MHz on top of that ?? To me, those kind of numbers look more like what we could expect of a new die-shrink to 0.09 micron. |
The demoed a working 2800+ chip, before the chip is even released at cebit(they didnt run it but Ill give amd the benifit of the doubt and say it was a working 2800+ chip.)
I see in my mind no pressing reason not to expect even faster tbreds than their PRERELEASE demo, ESPECIALLY since it appears the first batch on .13 isnt clocking well due to an error in their shrink(also the reason for the delay).
Now, everyone has given me the numbers, and they act as if they are waaay to high, but no one has given me a real physical reason why it is not going to be the case.
The axp core rearrangement gained almost 30% on the tbird due to a simple rearrangement, this is a core shrink, and I know people cant fathom a 2.5ghz tbred, but every bit of knowledge of semiconductors I have tells me that baring an unforseen factor(which I am asking everyone here for help in poining out) this will be the case.
| Quote : That still gives 320 real MHz on top of their demo version, not 200 MHz extra. 320MHz more on top of the already accomplished 400MHz ? |
The p4 willamette topped out at 2.2ghz, the shrink(and copperization) nets it a new top speed of around 3.5-3.6ghz(there are some 4ghz chips but they require super exotic cooling, but it just goes to show you what a shrink can do)
now intel is NOT doing anything different or magical over amd, their .13 shrink has no reason to work better. And the p4's design was ALREADY taken into account before the shrink(2.2ghz top compared to amds 1.8) and depending on how much gain copper added(I guess 10-15%) that should be how much amd gains.
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| Quote : Matisaro, could you enlighten me by explaining exactly WHAT the 0.13micron (0.18, 0.09...) refers to? Is it the absolutely smallest feature in the microprocessor, the gate-length, or what is it? |
In the industry feature size generally refers to the width of your smallest COMMON feature.
If you have a chip and its design causes it to have a few lines .13 microns appart, but the majority of them are .18 appart, then its a .18micron part.
The width of a feautre most generally is the width of the metal line AND the distance between them on the most dense layer(usually the first metal layer).
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| Quote : Aside from what you want to know, I've been wondering my entire life what and how the heck do they insert the transistors into such chips! I mean I've seen some in real life, but they were seeable, however these CPU transistors they speak of, are so small and packed, I wonder how they do them and what they look like! (55 Million in a small chip? man that is a lot and small) |
Basically they use photomasking and etching to make a silicon structure, then they connect it with metal and polysilicon to make a working functional unit.
For info on how a finished cpu works go <A HREF="http://www.howstuffworks.com/microprocessor.htm" target="_new">here</A>.
For info on how a fab makes semiconductors go <A HREF="http://www.howstuffworks.com/diode.htm" target="_new">here</A>.
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| Quote : Aren't the .13um sizes the size of the transisitors in the chip? The smaller they are, the more you could fit in a certain area and also this would decrease the amount of space you would need to contain a certain amount of transistors. |
The size of the iso-ox can be considered a feature, but the biggest gain from a process shrink is the smaller thinner COOLER lines, this is where the bulk of clockability comes from.(while transistors are smaller and faster as well dont get me wrong).
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| Quote : Next step is to put this through an etching process, which can be done by either 1) a chemical etch using some acid that attacks Silicon, but not the resist (or at least, not as fast); but the result of a "wet-etch" is often not desireable: it'll etch up against a crystal facet, and will most often NOT make square holes. Another approach is 2) a plasma-etching process (ECR), where a plasma is excited above the surface in a chamber filled with some combination of gases (Chlorine and Boron work for Gallium Arsenide; not sure about Si), and this approach can then be tuned to make pretty nice square holes, which is what you want. |
We have an educated person in the audience tonight, do you know what bugged me about the plasma etchers at fujitsu(and other fabs I would assume) THEY ARENT PLASMA, they are just radio stimulated matter, maybe im a geek, but the fact true plasma is about 10000 degrees(or thereabouts) and that it would melt the wafers just bugged me.
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So technically speaking you could have just one .13um thing in there and you could say that "this chip was made out of .13um proccess?" That doesn't sound right. I know you said that you worked at a fab before?, but still this is kinda weird..... maybe Prescott will only have one transistor that is .09um.
| Quote : Hmm, no, a wafer is just a thin pancake cut out of a long piece of Silicon. There's nothing in there but *pure* Silicon (as pure as possible). A transistor is like a LEGO construction on top of this wafer, composed of different layers of semiconductors, metals (for electrical contact) and insulators (for NO electrical contact). The difference between LEGO and semiconductor fabrication is that 1) Denmark has nothing to to with the latter and 2) there are no predefined pieces to put together in order to make a chip (or the transistors that it's composed of). |
Good analogy, but you left out doping, which changes the base silicon's(and polysilicon connections above it) electrical properties to actually form a transistor.
BTW, I dont know if I told you guys what I did at fujitsu, I was a yield enhancement specialist, I worked on "defects" and investigated them with a scanning electron microscope, very interesting stuff.
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| Quote : I'm not sure how the pipeline fits into it all... Does it increase the spacing between each transistor, although the transistors themselves might be small? It doesn't make much sense, but it could be true, I suppose...
|
Axctually you will hit a point where you are limited by the connections ot the outside, meaning you cant make the chip too small or you wont be able to package it for sale.(too many small gold wires, not enough space for contact pads).
Other than that, yes it is better to have smaller transistors.
(also I think that the more stages you have the LESS dense your transistors, because you would have alot of routing lines and distance between work units etc.)
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| Quote : Can anyone explain how the length of the pipeline affects the size of the transistor, or the size of the processor? |
The transistor size is a function of the process not the design, but the longer the pipe I want to say the less dense the transistors.
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| Quote : So technically speaking you could have just one .13um thing in there and you could say that "this chip was made out of .13um proccess?" That doesn't sound right. I know you said that you worked at a fab before?, but still this is kinda weird..... maybe Prescott will only have one transistor that is .09um. |
I did not say that, I said the exact opposite.
The feature size is the smallest size of a COMMON feature, not just one thing.
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This is what I said
| Quote : In the industry feature size generally refers to the width of your smallest COMMON feature.
|
And this is what you said.
| Quote : So technically speaking you could have just one .13um thing in there and you could say that "this chip was made out of .13um proccess?" |
Again with me
| Quote : If you have a chip and its design causes it to have a few lines .13 microns appart, but the majority of them are .18 appart, then its a .18micron part. |
Does not compute will robinson.
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