I just thought it was interesting that the second quarter estimates for AMD have been increased. I guess they must be lowering debt with 65nm. These price cuts should really be eating into the bottom line though. I will be interesting to see how things pan out when the results come out.

http://www.bloomberg.com/apps/news [...] fer=stocks

Well, if the forcasts are correct then that will be great news. I'm not a fan of AMD, but would really hate to see them bottom out. The competition really does benefit us comsumers by keeping innovation moving and keep prices reasonable. (Without presure from AMD we would probably have a Quad core P4, basically 2 P4D's stacked and connected, or something sad like that)

Heres hoping for a good launch for Barcy and a quick ATI product refresh

Its bad enough that we have to LAP our processors now... imagine if we didnt have AMD pretending there gunna come out with something better.

Go AMD even though i dont like you.

Wonder why AMD didn't follow Intel's lead right now and just connect to Athlon's to made a quad core to compete until Barcy comes out. While I respect that they want to take the time to do it right by making a native quad core, the dev time is causing a serious delay in release, hurting market share.

I remember when Intel came out with the PD and AMD stated that it wasn't a native dual core just two single cores connected together while theres was a native dual core. I remember reading the answer to that comment was, "it may not be pretty but it works for now."

The P4D wasn't a good option but it helped Intel keep a small amount of the market they may have lost while developing the C2D's.

I think the reason they don't do that might have something to do with the Uarch. I am not 100% sure, but it makes sense that it would be a little more difficult doing that with the mem controller on the die. Not sure though, just something I remember Jack saying a while back, before he left.

You probably know this: AMD use's an IMC. While the IMC is better for memory management, it doesnt lend itself to a MCM configuration nearly as well as Intels off die memory controller. Its would have been much more work for AMD to go the MCM route than it was for Intel. Additionally, AMD is still new to 65nm. The have been working on K10 prior to acheiveing 65nm. Making a quad on 90nm would have been hugely wastefull IRT die area, not to mention quad core chips on a 90nm die size would have had significant difficulties with heat.

There are some big advantages with MCM, that would have benefited AMD greatly had they been able to implement it. As far as the disadvantages, bus saturation and 'cache thrashing' so loudly 'hyped' by AMD and the fanboys; cache thrasing turned out to be nothing but BS hype, and bus stauration hasnt proven to be a problem.

If we didn't have AMD we would have something better than x86. It's over-the-hill now--let's duct tape on some more instructions. :lol

I knew of the ICM but didn't really take that into consideration with they way they seem to be able to turn off and on features just didn't think about it. Probably figured its not worth the effort or cost to modify the chips to do it. With intel planning on adding it I would think that the C2Q's could be the last of the stackers

I do hope Barcy will be a success and gives Intel a little nudge

(Note: I know Penryn (SP?) is coming soon, but ya never know where Barcy might make Intel change and/or improve, and then of course vise-versa)

There have been many threads about why AMD can't do an MCM (that would work well), so no point in rehashing that. But AMD *did* make two independent memory controllers in the 10h chips and that does allow for MCMs to be made while keeping the same sockets. (Each die would have one IMC active and one deactivated and communicate over an in-package HT link.) In fact, AMD has an eight-core MCM in their roadmap. I believe it is called "Montreal."

The cache thrashing did turn out to be a non-issue, but IIRC a shared L2 had never been done before and it didn't sound unreasonable. Bus saturation isn't much of an issue with the UP chips, but move to more sockets and cores and that becomes less and less true. By the time there are four dies on two FSBs in an Intel Clovertown dual-quad-core or Paxville MP quad-dual-core setup, bus saturation is certainly rearing its head versus a quad dual-core Opteron setup.


@Conroe: x86 probably isn't the world's greatest ISA and certainly wasn't when it debuted, but it has been modified enough to do the jobs we ask of it pretty decently. An all-new rewrite isn't necessarily better- the Itanium was and it is a pretty poor general-purpose CPU. There have been some instructions added, mostly in the form of SIMD ops, but I'd much rather have additional packed instructions like SSE rather than a one-operation-per-issue-per-clock-cycle pure RISC chip. And x86_64 cleaned up the old x86 ISA quite a bit as well. It's still not very nice to do assembly on, but assembly is generally only used for embeddable stuff today anyway.

finally those DELETED are getting back in business

I was wondering how long it would take for that to happen.

This could potentially be way of the mark. If I read right, Orji increased his second-quarter estimates for AMD on expectations of solid pc demand. Is he taking into account the recent market-share loss of AMD? If not, he's going to be well off the mark. I could be wrong here...guess we'll find out in the next few days.

On AMD's website, it appears you'll be able to watch their announcement of their 2Q '07 earnings at 4:00 p.m. eastern time on Thursday, July 19th.

http://phx.corporate-ir.net/phoeni [...] ails&c=740 93&eventID=1584412

More hype to get a $1 a share. Who was it they just bailed for 7.5 million?