This is a two-pronged question, that i'm not sure many will know the answer to.

1. How would Intel/AMD disable cache during manufacturing?

i.e. Say they have a Core2Duo chip that (at best) should have 4096KB's L2 cache. Let's say that 256K of that is non-functional, and therefore they disable a whole 2048KB's of cache, to end up with an Allendale(which they would obviously set to a lower multiplier...7x or 8x). How would they disable the cache(i'm assuming that cache is the same as Memory=Columns x Rows)?

2. This may be even harder to answer.

Say there is defective cache on the chip, would the defective "amounts" be random sizes.. i.e. 278KB, or would the defective areas be in amounts of say 64KB/128KB/256KB/512KB?

I've never seen any info on either of these questions, and i wonder if any of our resident process experts(possibly JJ, Joset, JkFlipFlop) or anyone else for that matter, knows the answer.

To be honest.

1.) I dunno

2.) I... dunno.

The question I have is.. to know that info, would you try to consider in re-activating the disabled cach?

That would be cool if you could. Even if you could get an Allendale up to 3MB cache. I highly doubt it's feasable, or people would be doing it already, and Conroe sales would really suffer.

O.o wouldn't that necessitate a clean room?

Probably.That wasn't the reason for my post anyways.... Just interested in the process.

I'd think that given that a fault can occur anywhere it could be a single gate that forms a bit, or it could be in an area that controls a a row or a column or a byte, and hence the fault could be any size.

The problem with re-enabling these is that you'd have to ensure that you knew precisley where the fault was and block it out so that it could not be used.

I wonder if the old days of unlocking multi's with a pencil might come back.

1. If I knew that then I would've attempted to try convert every Conroe-C(cut-down)/Allendale(unofficial) to Conroe...
...or not as I already do have a fair amount of clue how Intel does it and it's pretty extreme.

I'd think that given that a fault can occur anywhere it could be a single gate that forms a bit, or it could be in an area that controls a a row or a column or a byte, and hence the fault could be any size.

The problem with re-enabling these is that you'd have to ensure that you knew precisley where the fault was and block it out so that it could not be used.

I wonder if the old days of unlocking multi's with a pencil might come back.Too bad it wasn't easy like unlocking PS/VS on a GPU with software like Rivatuner.

Maybe they stuck a small pin through the die - just like my friend did with his flatmate's box of condoms 8O

That's no good. 8O

..and i'll follow that up with a.. oh jeezuz.

I seem to recall Jack discussing this a in thread not to long ago.

If I recall correctly, the chip has an internal "fuse". If the cache bank is defective, they overvolt that circuit and pop the fuse, permenantly locking of that cache.

I also recall they mentioned excess cache to compensate for bad cache.

Im sure JJ will be by with an accurate answer for ya soon enough

I seem to recall Jack discussing this a in thread not to long ago.

If I recall correctly, the chip has an internal "fuse". If the cache bank is defective, they overvolt that circuit and pop the fuse, permenantly locking of that cache.

I also recall they mentioned excess cache to compensate for bad cache.

Im sure JJ will be by with an accurate answer for ya soon enoughThanks... I kind of figured that if Jack knew how it was done, he would have explained it previously. I do seem to remember him mentioning something about redundancy WRT cache.

Hi!

Very interesting questions... it's darn late, here (5.15 am); I'll return tomorrow.


Cheers!

That's not late, that's early.

I look forward to your post. I figured it would be an interesting, yet little-known subject. Maybe the manufacturers classify that info as trade secrets, and therefore don't publish it? :?

The one that controls cache is also in the chip packaging area, I'm sure of it.
It's just that Intel and AMD have now found a way to hidden it from the surface to prevent modification.

I dont think they touch the Intel chip itself. I think it something to do underneath the chip. I could be wrong. But it a idea.

Just to point out the chip to the right upside down look at the center or the left next to the dual core.
http://www.anandtech.com/cpuchipse [...] spx?i=2866

If it was that easy it would've been modified in a blink of eye.
The fact Intel first found a way to lock multiplier/cache since P2 era meant it's a lot more than that.

There are thousands of wire traces in the chip packaging or the tiny gold wires that leads to the die itself. The lock would be on that path somewhere.
Well hidden with no way to bypass it(unlike the 100->133FSB pin bend mod )

1-They take a hammer and a nail and BANG, hit the area of cache to eliminate...this was too easy.
2-(I am serious here) No wonder that defective areas are random in size but since they are groupped in packages, like MB RAM, I guess you can't disable just say 16K of it just like you can't take out a chip from a RAM slot and still have it work. Even if they could do so, the result would be an incredible spectrum of products with variable specs (cache size), that is a marketing nightmare.